How to simulate a VHDL-AMS testbench without a schematic

VishwaVishwa Posts: 80
edited June 2016 in Saber Answers
Dear Terry,

I am writing with regard the simulation feature of SaberRD. I simulated a VHDL-AMS model based on the examples offered with the software, but I needed to convert this model to a symbol and then insert it into the schematic file. Although I could achieve simulating this model using some external signals as stimulus, placed in the schematic as well, I was wondering if there is the posibility to simulate the model directly from the testbench, without employing the schematic file.I will be grateful if you could deliver me this information.

Yours sincerely,
Luighi Vitón

Comments

  • VishwaVishwa Posts: 80
    Hello Luighi,

    I am Vishwa from Saber group in India.

    Thank you for choosing SaberRD Student Edition.
    In SaberRDS, please open the desired design (schematic). A design / schematic is required at the first time,

    Then, goto File > Open > Open Design and change the file type to "Create Design from HDL file".
    You can then choose <name>.ai_vhddsn file which opens this netlist inside SaberRD.
    Then you can perform simulation, analysis on this netlist without employing the schematic file.

    Please see the attached snapshot.

    I hope this helps.

    Thanks and Regards.
    Vishwa
  • VishwaVishwa Posts: 80

    Hello Vishwa,

    I followed your steps and I could simulate directly from the code as I wanted in the beginning. Thank you for your help.
    I attached a report file regarding the process I followed. It could be helpful to someone else who wanted to simulate from a custom design.
    Thanks again for your time,

    Best regards,
     
    Luighi Anthony Vitón Zorrilla
    INICTEL-UNI
    Lima, Perú

    ----- Mensaje original -----
    Hello Luighi,


    For VHDL-AMS models that are custom made, example “multiplexer.vhd”, they need to in a library before being used.

    Can you please open a dummy design and create a new library ? Library can be created in Libraries tab.
    And then you can add the .vhd models (not testbench) to the library and compile the library.
    You can then open the testbench file and do a simulation.

    Please try the above and let me know if you have any questions.


    Thanks,
    Vishwa

Sign In or Register to comment.