Stability Analysis using Periodic Small-Signal AC and Pole-Zero Analyses

Datsen Davies Tharakan

Introduction

Stability of a linear system can be evaluated using several geometrical techniques like Nyquist plot, Root Locus Plot, and Bode plot. In this design example, stability of closed loop control of a buck converter is investigated using Root Locus plot and Bode plot with the help of Pole-Zero (PZ) analysis and Periodic small-signal AC (PAC) analysis, respectively. The results from the PZ analysis gives the location of poles and zeroes of the transfer function of the system and helps to predict the stability of the system. If the location of poles is on the left hand side of the Root Locus plot, the system is said to be stable. PAC analysis will provide frequency response of the system in Bode plot from which the gain and phase margins can be measured. Gain and phase margins determine the stability margins of the system. Theoretically, a system is said to be stable if both gain and phase margins have positive values. But for a power circuit design, 45° is often taken as a minimum goal for the phase margin. The controller models in the buck converter design discussed here, are based on VHDL-AMS modeling language created using StateAMS modeling tool. 
This design example can be used to demonstrate,

• Usability of StateAMS tool to create behavioral level control components.

• Discrete control of converter using models created from StateAMS tool.

• Applicability of Periodic small-signal AC (PAC) analysis and Pole-Zero (PZ) analysis to check the stability criteria of a power circuit design.

How to use the example:

Download the attached " stability_analysis_using_PAC_PZ.zip" and unzip to a local folder. Open the buck_converter_5V_25W.ai_dsn in SaberRD and run the experiments listed in the Experiment Analyzer.

For more details of the design, how to run the design, etc., refer to the README.pdf file in the attachments.

Note: This design example works only in SaberRD commercial edition 2017.12 and above.

Circuit Diagram: